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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_i2s_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__i2s.html">I2S          (Inter-IC Sound)</a> &raquo; <a class="el" href="group__group__i2s__data__structures.html">Data Structures</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>I2S initialization configuration. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ae8ca5293003aa3425e04539009983b1f"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#ae8ca5293003aa3425e04539009983b1f">txEnabled</a></td></tr>
<tr class="memdesc:ae8ca5293003aa3425e04539009983b1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the I2S TX component: 'false': disabled.  <a href="#ae8ca5293003aa3425e04539009983b1f">More...</a><br /></td></tr>
<tr class="separator:ae8ca5293003aa3425e04539009983b1f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad64295a93c1741f430b572eb0a402ede"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#ad64295a93c1741f430b572eb0a402ede">rxEnabled</a></td></tr>
<tr class="memdesc:ad64295a93c1741f430b572eb0a402ede"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the I2S RX component: 'false': disabled.  <a href="#ad64295a93c1741f430b572eb0a402ede">More...</a><br /></td></tr>
<tr class="separator:ad64295a93c1741f430b572eb0a402ede"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a92218e90b918ad769b857376fd322f3b"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a92218e90b918ad769b857376fd322f3b">txDmaTrigger</a></td></tr>
<tr class="memdesc:a92218e90b918ad769b857376fd322f3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">'false': TX DMA trigger disabled, 'true': TX DMA trigger enabled.  <a href="#a92218e90b918ad769b857376fd322f3b">More...</a><br /></td></tr>
<tr class="separator:a92218e90b918ad769b857376fd322f3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a665012e429f01ec28f34eeb4aa1879c9"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a665012e429f01ec28f34eeb4aa1879c9">rxDmaTrigger</a></td></tr>
<tr class="memdesc:a665012e429f01ec28f34eeb4aa1879c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">'false': RX DMA trigger disabled, 'true': RX DMA trigger enabled.  <a href="#a665012e429f01ec28f34eeb4aa1879c9">More...</a><br /></td></tr>
<tr class="separator:a665012e429f01ec28f34eeb4aa1879c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac207745366dbc76ad317e3e9ef30a231"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#ac207745366dbc76ad317e3e9ef30a231">clkDiv</a></td></tr>
<tr class="memdesc:ac207745366dbc76ad317e3e9ef30a231"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, ..., 64: 1/64.  <a href="#ac207745366dbc76ad317e3e9ef30a231">More...</a><br /></td></tr>
<tr class="separator:ac207745366dbc76ad317e3e9ef30a231"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4b3e4ecb0a2da20efdba370dc8696534"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a4b3e4ecb0a2da20efdba370dc8696534">extClk</a></td></tr>
<tr class="memdesc:a4b3e4ecb0a2da20efdba370dc8696534"><td class="mdescLeft">&#160;</td><td class="mdescRight">'false': internal clock, 'true': external clock.  <a href="#a4b3e4ecb0a2da20efdba370dc8696534">More...</a><br /></td></tr>
<tr class="separator:a4b3e4ecb0a2da20efdba370dc8696534"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:affb22af190ce98c200f23fec3dcad294"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#affb22af190ce98c200f23fec3dcad294">txMasterMode</a></td></tr>
<tr class="memdesc:affb22af190ce98c200f23fec3dcad294"><td class="mdescLeft">&#160;</td><td class="mdescRight">'false': TX in slave mode, 'true': TX in master mode.  <a href="#affb22af190ce98c200f23fec3dcad294">More...</a><br /></td></tr>
<tr class="separator:affb22af190ce98c200f23fec3dcad294"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5f3d11cd3e68da381d548c3a98b52e36"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__i2s__enums.html#gac2ba15c8dab8fc0c422ab369992636f5">cy_en_i2s_alignment_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a5f3d11cd3e68da381d548c3a98b52e36">txAlignment</a></td></tr>
<tr class="memdesc:a5f3d11cd3e68da381d548c3a98b52e36"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX data alignment, see: <a class="el" href="group__group__i2s__enums.html#gac2ba15c8dab8fc0c422ab369992636f5" title="I2S data alignment. ">cy_en_i2s_alignment_t</a>.  <a href="#a5f3d11cd3e68da381d548c3a98b52e36">More...</a><br /></td></tr>
<tr class="separator:a5f3d11cd3e68da381d548c3a98b52e36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac57fdc45c9e083bcac17e1ca847f6015"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__i2s__enums.html#ga265f4e0f0d40f96b383a91aab3215f79">cy_en_i2s_ws_pw_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#ac57fdc45c9e083bcac17e1ca847f6015">txWsPulseWidth</a></td></tr>
<tr class="memdesc:ac57fdc45c9e083bcac17e1ca847f6015"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX Word Select pulse width.  <a href="#ac57fdc45c9e083bcac17e1ca847f6015">More...</a><br /></td></tr>
<tr class="separator:ac57fdc45c9e083bcac17e1ca847f6015"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a54bd9fc3bd281f932228198aa943cc9e"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a54bd9fc3bd281f932228198aa943cc9e">txWatchdogEnable</a></td></tr>
<tr class="memdesc:a54bd9fc3bd281f932228198aa943cc9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">'false': TX watchdog disabled, 'true': TX watchdog enabled.  <a href="#a54bd9fc3bd281f932228198aa943cc9e">More...</a><br /></td></tr>
<tr class="separator:a54bd9fc3bd281f932228198aa943cc9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a10cc840e19829c3e2cdc97a30ff34f64"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a10cc840e19829c3e2cdc97a30ff34f64">txWatchdogValue</a></td></tr>
<tr class="memdesc:a10cc840e19829c3e2cdc97a30ff34f64"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX watchdog counter value (32 bit).  <a href="#a10cc840e19829c3e2cdc97a30ff34f64">More...</a><br /></td></tr>
<tr class="separator:a10cc840e19829c3e2cdc97a30ff34f64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7fba051342abb74bf11d42973ef7f34e"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a7fba051342abb74bf11d42973ef7f34e">txSdoLatchingTime</a></td></tr>
<tr class="memdesc:a7fba051342abb74bf11d42973ef7f34e"><td class="mdescLeft">&#160;</td><td class="mdescRight">'false': SDO bit starts at falling edge (accordingly to the I2S Standard, if txSckoInversion is false), 'true': SDO bit starts at rising edge which goes before the above mentioned falling edge, i.e.  <a href="#a7fba051342abb74bf11d42973ef7f34e">More...</a><br /></td></tr>
<tr class="separator:a7fba051342abb74bf11d42973ef7f34e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7beded187a0628a3fb8e279e3216e5ab"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a7beded187a0628a3fb8e279e3216e5ab">txSckoInversion</a></td></tr>
<tr class="memdesc:a7beded187a0628a3fb8e279e3216e5ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX SCKO polarity: 'false': When transmitter is in master mode, serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); 'true': When transmitter is in master mode, serial data is transmitted off the rising bit clock edge.  <a href="#a7beded187a0628a3fb8e279e3216e5ab">More...</a><br /></td></tr>
<tr class="separator:a7beded187a0628a3fb8e279e3216e5ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa3424ecb0bdcc37376ab78f3732c9ba9"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#aa3424ecb0bdcc37376ab78f3732c9ba9">txSckiInversion</a></td></tr>
<tr class="memdesc:aa3424ecb0bdcc37376ab78f3732c9ba9"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX SCKI polarity: 'false': When transmitter is in slave mode, serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); 'true': When transmitter is in slave mode, serial data is transmitted off the rising bit clock edge.  <a href="#aa3424ecb0bdcc37376ab78f3732c9ba9">More...</a><br /></td></tr>
<tr class="separator:aa3424ecb0bdcc37376ab78f3732c9ba9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad805d382b09d9bdb91c923f874ae0b37"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#ad805d382b09d9bdb91c923f874ae0b37">txChannels</a></td></tr>
<tr class="memdesc:ad805d382b09d9bdb91c923f874ae0b37"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of TX channels, valid range is 1...8 for TDM modes.  <a href="#ad805d382b09d9bdb91c923f874ae0b37">More...</a><br /></td></tr>
<tr class="separator:ad805d382b09d9bdb91c923f874ae0b37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a703d047350ed1d0f1f953afc3a865ee6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630">cy_en_i2s_len_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a703d047350ed1d0f1f953afc3a865ee6">txChannelLength</a></td></tr>
<tr class="memdesc:a703d047350ed1d0f1f953afc3a865ee6"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX channel length, see <a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630" title="I2S channel/word length. ">cy_en_i2s_len_t</a>, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes.  <a href="#a703d047350ed1d0f1f953afc3a865ee6">More...</a><br /></td></tr>
<tr class="separator:a703d047350ed1d0f1f953afc3a865ee6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadfece214c934881a93cb49090b31aeb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630">cy_en_i2s_len_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#aadfece214c934881a93cb49090b31aeb">txWordLength</a></td></tr>
<tr class="memdesc:aadfece214c934881a93cb49090b31aeb"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX word length, see <a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630" title="I2S channel/word length. ">cy_en_i2s_len_t</a>, must be less or equal to txChannelLength.  <a href="#aadfece214c934881a93cb49090b31aeb">More...</a><br /></td></tr>
<tr class="separator:aadfece214c934881a93cb49090b31aeb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a78b11b9c26fe6e733f639ae22339d1df"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__i2s__enums.html#gace34f02636657f8a8f1290fcbc5acfa6">cy_en_i2s_overhead_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a78b11b9c26fe6e733f639ae22339d1df">txOverheadValue</a></td></tr>
<tr class="memdesc:a78b11b9c26fe6e733f639ae22339d1df"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX overhead bits value when the word length is less than the channel length.  <a href="#a78b11b9c26fe6e733f639ae22339d1df">More...</a><br /></td></tr>
<tr class="separator:a78b11b9c26fe6e733f639ae22339d1df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aea3ab9716a65392148d0d72c6566c200"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#aea3ab9716a65392148d0d72c6566c200">txFifoTriggerLevel</a></td></tr>
<tr class="memdesc:aea3ab9716a65392148d0d72c6566c200"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX FIFO interrupt trigger level (0, 1, ..., 255).  <a href="#aea3ab9716a65392148d0d72c6566c200">More...</a><br /></td></tr>
<tr class="separator:aea3ab9716a65392148d0d72c6566c200"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab294c0a490bef99f8160e3210c3e364d"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#ab294c0a490bef99f8160e3210c3e364d">rxMasterMode</a></td></tr>
<tr class="memdesc:ab294c0a490bef99f8160e3210c3e364d"><td class="mdescLeft">&#160;</td><td class="mdescRight">'false': RX in slave mode, 'true': RX in master mode.  <a href="#ab294c0a490bef99f8160e3210c3e364d">More...</a><br /></td></tr>
<tr class="separator:ab294c0a490bef99f8160e3210c3e364d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9357093696a0b9836a743e9b265dab4b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__i2s__enums.html#gac2ba15c8dab8fc0c422ab369992636f5">cy_en_i2s_alignment_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a9357093696a0b9836a743e9b265dab4b">rxAlignment</a></td></tr>
<tr class="memdesc:a9357093696a0b9836a743e9b265dab4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX data alignment, see: <a class="el" href="group__group__i2s__enums.html#gac2ba15c8dab8fc0c422ab369992636f5" title="I2S data alignment. ">cy_en_i2s_alignment_t</a>.  <a href="#a9357093696a0b9836a743e9b265dab4b">More...</a><br /></td></tr>
<tr class="separator:a9357093696a0b9836a743e9b265dab4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a68d16581b84a75a1272a467efb185b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__i2s__enums.html#ga265f4e0f0d40f96b383a91aab3215f79">cy_en_i2s_ws_pw_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a1a68d16581b84a75a1272a467efb185b">rxWsPulseWidth</a></td></tr>
<tr class="memdesc:a1a68d16581b84a75a1272a467efb185b"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX Word Select pulse width.  <a href="#a1a68d16581b84a75a1272a467efb185b">More...</a><br /></td></tr>
<tr class="separator:a1a68d16581b84a75a1272a467efb185b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6cfbaa5285dcb6884dcff3c660719f67"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a6cfbaa5285dcb6884dcff3c660719f67">rxWatchdogEnable</a></td></tr>
<tr class="memdesc:a6cfbaa5285dcb6884dcff3c660719f67"><td class="mdescLeft">&#160;</td><td class="mdescRight">'false': RX watchdog disabled, 'true': RX watchdog enabled.  <a href="#a6cfbaa5285dcb6884dcff3c660719f67">More...</a><br /></td></tr>
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<tr class="memitem:ad7d2c281ce7a33143060b87e8747bc87"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#ad7d2c281ce7a33143060b87e8747bc87">rxWatchdogValue</a></td></tr>
<tr class="memdesc:ad7d2c281ce7a33143060b87e8747bc87"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX watchdog counter value (32 bit).  <a href="#ad7d2c281ce7a33143060b87e8747bc87">More...</a><br /></td></tr>
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<tr class="memitem:a90bf0e2ed57f80d21401ff1ffb1ab255"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a90bf0e2ed57f80d21401ff1ffb1ab255">rxSdiLatchingTime</a></td></tr>
<tr class="memdesc:a90bf0e2ed57f80d21401ff1ffb1ab255"><td class="mdescLeft">&#160;</td><td class="mdescRight">'false': SDI bit starts at falling edge (accordingly to the I2S Standard if rxSckoInversion is false), 'true': SDI bit starts at rising edge that goes after the above mentioned falling edge, i.e.  <a href="#a90bf0e2ed57f80d21401ff1ffb1ab255">More...</a><br /></td></tr>
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<tr class="memitem:a3e1fd9c47933fafb97f2a5db7c17a124"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a3e1fd9c47933fafb97f2a5db7c17a124">rxSckoInversion</a></td></tr>
<tr class="memdesc:a3e1fd9c47933fafb97f2a5db7c17a124"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX SCKO polarity: 'false': When receiver is in master mode, serial data is captured by the rising bit clock edge (accordingly to the I2S Standard); 'true': When receiver is in master mode, serial data is captured by the falling bit clock edge.  <a href="#a3e1fd9c47933fafb97f2a5db7c17a124">More...</a><br /></td></tr>
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<tr class="memitem:aae28c44edbb22ae19829f618d4ca63e2"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#aae28c44edbb22ae19829f618d4ca63e2">rxSckiInversion</a></td></tr>
<tr class="memdesc:aae28c44edbb22ae19829f618d4ca63e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX SCKI polarity: 'false': When receiver is in slave mode, serial data is captured by the rising bit clock edge (accordingly to the I2S Standard); 'true': When receiver is in slave mode, serial data is captured by the falling bit clock edge.  <a href="#aae28c44edbb22ae19829f618d4ca63e2">More...</a><br /></td></tr>
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<tr class="memitem:a8fef75cbb357474afc343319c494d6ba"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a8fef75cbb357474afc343319c494d6ba">rxChannels</a></td></tr>
<tr class="memdesc:a8fef75cbb357474afc343319c494d6ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of RX channels, valid range is 1...8 for TDM modes.  <a href="#a8fef75cbb357474afc343319c494d6ba">More...</a><br /></td></tr>
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<tr class="memitem:a07159a66943e174da0fe8399b1c92ecf"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630">cy_en_i2s_len_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a07159a66943e174da0fe8399b1c92ecf">rxChannelLength</a></td></tr>
<tr class="memdesc:a07159a66943e174da0fe8399b1c92ecf"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX channel length, see <a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630" title="I2S channel/word length. ">cy_en_i2s_len_t</a>, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes.  <a href="#a07159a66943e174da0fe8399b1c92ecf">More...</a><br /></td></tr>
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<tr class="memitem:a86d1bba1ff1b263a56a34676a02f33a5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630">cy_en_i2s_len_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a86d1bba1ff1b263a56a34676a02f33a5">rxWordLength</a></td></tr>
<tr class="memdesc:a86d1bba1ff1b263a56a34676a02f33a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX word length, see <a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630" title="I2S channel/word length. ">cy_en_i2s_len_t</a>, must be less or equal to rxChannelLength.  <a href="#a86d1bba1ff1b263a56a34676a02f33a5">More...</a><br /></td></tr>
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<tr class="memitem:a32ee6420329993e3409942dec1073102"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a32ee6420329993e3409942dec1073102">rxSignExtension</a></td></tr>
<tr class="memdesc:a32ee6420329993e3409942dec1073102"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX value sign extension (when the word length is less than 32 bits), 'false': all MSB are filled by zeroes, 'true': all MSB are filled by the original sign bit value.  <a href="#a32ee6420329993e3409942dec1073102">More...</a><br /></td></tr>
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<tr class="memitem:a1121d3c9611fc8d4e1cc81a90a2d9e51"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__i2s__config__t.html#a1121d3c9611fc8d4e1cc81a90a2d9e51">rxFifoTriggerLevel</a></td></tr>
<tr class="memdesc:a1121d3c9611fc8d4e1cc81a90a2d9e51"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX FIFO interrupt trigger level (0, 1, ..., (255 - (number of channels))).  <a href="#a1121d3c9611fc8d4e1cc81a90a2d9e51">More...</a><br /></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#ae8ca5293003aa3425e04539009983b1f">&#9670;&nbsp;</a></span>txEnabled</h2>

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<p>Enables the I2S TX component: 'false': disabled. </p>
<p>'true': enabled. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad64295a93c1741f430b572eb0a402ede">&#9670;&nbsp;</a></span>rxEnabled</h2>

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<p>Enables the I2S RX component: 'false': disabled. </p>
<p>'true': enabled. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a92218e90b918ad769b857376fd322f3b">&#9670;&nbsp;</a></span>txDmaTrigger</h2>

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<p>'false': TX DMA trigger disabled, 'true': TX DMA trigger enabled. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a665012e429f01ec28f34eeb4aa1879c9">&#9670;&nbsp;</a></span>rxDmaTrigger</h2>

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<p>'false': RX DMA trigger disabled, 'true': RX DMA trigger enabled. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac207745366dbc76ad317e3e9ef30a231">&#9670;&nbsp;</a></span>clkDiv</h2>

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<p>CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, ..., 64: 1/64. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4b3e4ecb0a2da20efdba370dc8696534">&#9670;&nbsp;</a></span>extClk</h2>

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<p>'false': internal clock, 'true': external clock. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#affb22af190ce98c200f23fec3dcad294">&#9670;&nbsp;</a></span>txMasterMode</h2>

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<p>'false': TX in slave mode, 'true': TX in master mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5f3d11cd3e68da381d548c3a98b52e36">&#9670;&nbsp;</a></span>txAlignment</h2>

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          <td class="memname"><a class="el" href="group__group__i2s__enums.html#gac2ba15c8dab8fc0c422ab369992636f5">cy_en_i2s_alignment_t</a> cy_stc_i2s_config_t::txAlignment</td>
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<p>TX data alignment, see: <a class="el" href="group__group__i2s__enums.html#gac2ba15c8dab8fc0c422ab369992636f5" title="I2S data alignment. ">cy_en_i2s_alignment_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac57fdc45c9e083bcac17e1ca847f6015">&#9670;&nbsp;</a></span>txWsPulseWidth</h2>

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<p>TX Word Select pulse width. </p>
<p>The value of this parameter is ignored in I2S and Left Justified modes the WS pulse width is always "one channel length" in these modes. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a54bd9fc3bd281f932228198aa943cc9e">&#9670;&nbsp;</a></span>txWatchdogEnable</h2>

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<p>'false': TX watchdog disabled, 'true': TX watchdog enabled. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a10cc840e19829c3e2cdc97a30ff34f64">&#9670;&nbsp;</a></span>txWatchdogValue</h2>

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<p>TX watchdog counter value (32 bit). </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7fba051342abb74bf11d42973ef7f34e">&#9670;&nbsp;</a></span>txSdoLatchingTime</h2>

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<p>'false': SDO bit starts at falling edge (accordingly to the I2S Standard, if txSckoInversion is false), 'true': SDO bit starts at rising edge which goes before the above mentioned falling edge, i.e. </p>
<p>the SDO signal is advanced by 0.5 SCK period (if txSckoInversion is false). If txSckoInversion is true - the rising/falling edges just swaps in above explanations. Effective only in slave mode, must be false in master mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7beded187a0628a3fb8e279e3216e5ab">&#9670;&nbsp;</a></span>txSckoInversion</h2>

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<p>TX SCKO polarity: 'false': When transmitter is in master mode, serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); 'true': When transmitter is in master mode, serial data is transmitted off the rising bit clock edge. </p>
<p>Effective only in master mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa3424ecb0bdcc37376ab78f3732c9ba9">&#9670;&nbsp;</a></span>txSckiInversion</h2>

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<p>TX SCKI polarity: 'false': When transmitter is in slave mode, serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); 'true': When transmitter is in slave mode, serial data is transmitted off the rising bit clock edge. </p>
<p>Effective only in slave mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad805d382b09d9bdb91c923f874ae0b37">&#9670;&nbsp;</a></span>txChannels</h2>

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<p>Number of TX channels, valid range is 1...8 for TDM modes. </p>
<p>In the I2S and Left Justified modes the value of this parameter is ignored - the real number of channels is always 2 in these modes. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a703d047350ed1d0f1f953afc3a865ee6">&#9670;&nbsp;</a></span>txChannelLength</h2>

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          <td class="memname"><a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630">cy_en_i2s_len_t</a> cy_stc_i2s_config_t::txChannelLength</td>
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<p>TX channel length, see <a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630" title="I2S channel/word length. ">cy_en_i2s_len_t</a>, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aadfece214c934881a93cb49090b31aeb">&#9670;&nbsp;</a></span>txWordLength</h2>

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          <td class="memname"><a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630">cy_en_i2s_len_t</a> cy_stc_i2s_config_t::txWordLength</td>
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<p>TX word length, see <a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630" title="I2S channel/word length. ">cy_en_i2s_len_t</a>, must be less or equal to txChannelLength. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a78b11b9c26fe6e733f639ae22339d1df">&#9670;&nbsp;</a></span>txOverheadValue</h2>

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<p>TX overhead bits value when the word length is less than the channel length. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aea3ab9716a65392148d0d72c6566c200">&#9670;&nbsp;</a></span>txFifoTriggerLevel</h2>

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<p>TX FIFO interrupt trigger level (0, 1, ..., 255). </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab294c0a490bef99f8160e3210c3e364d">&#9670;&nbsp;</a></span>rxMasterMode</h2>

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<p>'false': RX in slave mode, 'true': RX in master mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a9357093696a0b9836a743e9b265dab4b">&#9670;&nbsp;</a></span>rxAlignment</h2>

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<p>RX data alignment, see: <a class="el" href="group__group__i2s__enums.html#gac2ba15c8dab8fc0c422ab369992636f5" title="I2S data alignment. ">cy_en_i2s_alignment_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a1a68d16581b84a75a1272a467efb185b">&#9670;&nbsp;</a></span>rxWsPulseWidth</h2>

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<p>RX Word Select pulse width. </p>
<p>The value of this parameter is ignored in I2S and Left Justified modes the WS pulse width is always "one channel length" in these modes. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6cfbaa5285dcb6884dcff3c660719f67">&#9670;&nbsp;</a></span>rxWatchdogEnable</h2>

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<p>'false': RX watchdog disabled, 'true': RX watchdog enabled. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad7d2c281ce7a33143060b87e8747bc87">&#9670;&nbsp;</a></span>rxWatchdogValue</h2>

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<p>RX watchdog counter value (32 bit). </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a90bf0e2ed57f80d21401ff1ffb1ab255">&#9670;&nbsp;</a></span>rxSdiLatchingTime</h2>

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<p>'false': SDI bit starts at falling edge (accordingly to the I2S Standard if rxSckoInversion is false), 'true': SDI bit starts at rising edge that goes after the above mentioned falling edge, i.e. </p>
<p>the SDI signal is delayed by 0.5 SCK period (if rxSckoInversion is false). If rxSckoInversion is true - the rising/falling edges just swaps in above explanations. Effective only in master mode, must be false in slave mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a3e1fd9c47933fafb97f2a5db7c17a124">&#9670;&nbsp;</a></span>rxSckoInversion</h2>

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<p>RX SCKO polarity: 'false': When receiver is in master mode, serial data is captured by the rising bit clock edge (accordingly to the I2S Standard); 'true': When receiver is in master mode, serial data is captured by the falling bit clock edge. </p>
<p>Effective only in master mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aae28c44edbb22ae19829f618d4ca63e2">&#9670;&nbsp;</a></span>rxSckiInversion</h2>

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<p>RX SCKI polarity: 'false': When receiver is in slave mode, serial data is captured by the rising bit clock edge (accordingly to the I2S Standard); 'true': When receiver is in slave mode, serial data is captured by the falling bit clock edge. </p>
<p>Effective only in slave mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a8fef75cbb357474afc343319c494d6ba">&#9670;&nbsp;</a></span>rxChannels</h2>

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<p>Number of RX channels, valid range is 1...8 for TDM modes. </p>
<p>In the I2S and Left Justified modes the value of this parameter is ignored - the real number of channels is always 2 in these modes. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a07159a66943e174da0fe8399b1c92ecf">&#9670;&nbsp;</a></span>rxChannelLength</h2>

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          <td class="memname"><a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630">cy_en_i2s_len_t</a> cy_stc_i2s_config_t::rxChannelLength</td>
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<p>RX channel length, see <a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630" title="I2S channel/word length. ">cy_en_i2s_len_t</a>, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a86d1bba1ff1b263a56a34676a02f33a5">&#9670;&nbsp;</a></span>rxWordLength</h2>

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<p>RX word length, see <a class="el" href="group__group__i2s__enums.html#ga23a77f23cf018c0a0ca3874a0709a630" title="I2S channel/word length. ">cy_en_i2s_len_t</a>, must be less or equal to rxChannelLength. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a32ee6420329993e3409942dec1073102">&#9670;&nbsp;</a></span>rxSignExtension</h2>

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<p>RX value sign extension (when the word length is less than 32 bits), 'false': all MSB are filled by zeroes, 'true': all MSB are filled by the original sign bit value. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a1121d3c9611fc8d4e1cc81a90a2d9e51">&#9670;&nbsp;</a></span>rxFifoTriggerLevel</h2>

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<p>RX FIFO interrupt trigger level (0, 1, ..., (255 - (number of channels))). </p>

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